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Project Oberon FPGA RISC5 Workstation

SDHC Disk Image (July 2018)


  1. Introduction
  2. Enhancements
  3. New Features, Library Modules and Functions
  4. New Source Code Examples
  5. Supported Development Boards
  7. Technical Support

1. Introduction

The Project Oberon Workstation operating system is described in an article titled Oberon System Implemented on a Low-Cost FPGA Board which was published in Issue 91, Second Quarter 2015, of Xilinx's Xcell Journal.

We distribute an enhanced version of the Oberon compiler, executable and source code files of the Project Oberon operating system on an SDHC disk image for no charge. This is for the convenience of those who want to use Project Oberon on an actual FPGAdevelopemnt board 'out-of-the-box'.

Similar disk images are available from the Project Oberon and board manufacturers' sites but, at the time this page was last updated, they had not been brought up to date with the latest source code available.

The additional features and new library modules which are described below.

Once you have installed the image on an SDHC card you can use it to boot and run the Project Oberon workstation system on an FPGA development board that has been programmed with the RISC5 Verilog files which are also included with the disk image.

Oberon software development can then be carried out using Project Oberon's screen editing and compilation features without using Astrobe, Windows or any other operating system.

An alternative approach is to use Astrobe for FPGA RISC5, a free Windows 10 development system that developers can use to edit and cross-compile Oberon applications. The compiled applications produced by Astrobe can be uploaded to the host FPGA RISC5 target development board via a fast RS232 link from the PC to run on a subset of Project Oberon 2013. Go to the Embedded Project Oberon page for more information .

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2. Enhancements

There are a number of differences between the implementation of Project Oberon that can be downloaded here and the standard Project Oberon workstation system:

  • The Project Oberon bootloader always boots from the SDHC drive - there is no need to configure any switches. Booting via RS232 is not supported.
  • The Oberon compiler supports CASE statements with INTEGER or CHAR expressions. Hence it is fully compliant with the latest May 2016 revision of the Oberon Language Report.
  • The RISC5 instruction set includes an extension of the Branch Conditional instruction. This extension was introduced to allow the efficient implementation of CASE statements.
  • The Oberon command Upload.Run can be used with the Astrobe for FPGA RISC5 Terminal program to transfer files from your Windows PC to Project Oberon. This replaces the original Plink1 application. HCFiler (see below) is used to transfer files in the opposite direction.
  • The timestamps on files that are uploaded from Windows using Upload are preserved on the Project Oberon file system to allow for file synchronisation between the two systems.

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3. New Features, Library Modules and Functions


Interrupts are implemented as described in the latest Project Oberon changes (dated 15 Jun 2018).


HCFiler was developed for Project Oberon to be used for data logging, backups, transferring files to a PC etc. It can be used to create files with a total size exceeding the 64 MB limit of the standard Project Oberon SD card file system. Those files can subsequently be processed / analysed on a Windows system.


The modules RTC and SPI1 contain functions which provide support in RISC5 Project Oberon for the Maxim DS3234 Real-Time Clock device. The DS3234 is a battery-backed chip that provides continuous time (hours, minutes and seconds) and date (year, month and day) information accurate to +/- 2 minutes per year via an SPI interface. As well as providing the ability to automatically timestamp Project Oberon files it can be used with the Astrobe HCFiler file system functions to implement accurate datalogging applications.

The RTC device is available as a convenient Deadon RTC breakout board from SparkFun. Comparable devices may be substituted just by customising the RTC module. It is not necessary to modify the Kernel or rebuild the OS core.


If a functioning RTC device is detected at system startup time the new Kernel procedures InstallClock and InstallSetClock are used to assign RTC.Clock and RTC.SetClock to the corresponding Kernel procedure variables. Any calls to Kernel.Clock then return the time retrieved from the RTC device. Hence, files subsequently created by Project Oberon are correctly timestamped.

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4. New Source Code Examples

New source code examples include:

  • TestInt:
    • On - Enables interrupts. An interrupt handler is installed when the module is loaded. When interrupts are enabled the handler is invoked every 500 ms to blink an LED.
    • Off - Disables interrupts. The LED stops blinking.
  • HCTools:
    • InitDisk - Initialise an HCFiler file system on an SDHC card. Any existing HCFiler files will subsequently be inaccessible.
    • WriteFiles - Copy files from a Project Oberon file system to an HCFiler file system on the same SDHC card and
    • Dir - Display a list of HCFiler files on the SDHC Card.
  • DateTime:
    • ShowDate - Display the current date using the RTC library module.
    • ShowTime - Display the current time using the RTC library module.
  • Temperature:
    • Show - Display the temperature read from the DS3234 Real-Time Clock peripheral device.
  • Soundex:
    • Run - Compare the performance of numeric CASE statements vs. the equivalent IF-THEN-ELSE statements.
  • SwitchTest
    • Run - Displays a list of switches that are on.
  • ButtonTest
    • Run - Loops infinitely. When a button is pressed the button number is displayed and the program terminates.

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5. Supported Development Boards

A  Project Oberon Workstation SDHC image and Verilog sources are currently available free of charge for:

Board FPGA Part Manufacturer
Pepino LX9 Spartan-6 XC6SLX9 Saanlima

The following boards are no longer available from the manufacturer. We will make a download package available for existing users of a board if there is sufficient demand (i.e. three or more requests received), or if the board is subsequently made available again.

Board FPGA Part Manufacturer
Pepino LX25 Spartan-6 XC6SLX25 Saanlima
Pipistrello Spartan-6 XC6SLX45 Saanlima
OberonStation Spartan-3 XC3S700AN enso

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The complete Project Oberon FPGA RISC5 Workstation software system consists of: 

  • A MicroSDHC disk image file containing the Project Oberon OS with sources
  • A bitstream file to program the RISC5 processor on the target FPGA processor
  • Verilog sources to customise the RISC5 system if desired

Request your copy via email You should receive an email with your download instructions within 2 business days.

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7. Technical Support

If you have any questions about this system ask them on the Astrobe for FPGA RISC5 Forum. You will also find the latest news and implementation details there. 

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