Astrobe Forum

The Nexys.xcd file - to my knowledge - defines the periphery of the Artix FPGA, which means the pinout.

Now i'm really wondering where the memory link (inbus, outbus, adressbus) is set? i simply find no definition for it in the file?

Raspberry Pi have defined Metadata Blocks to be used to configure RP2350 applications. These blocks are embedded in the executable UF2 format file. Details of these blocks can be seen in Section 5.9 of the RP2350 DataSheet. The initial release of Astrobe for RP2350 implemented an Image Def block usi...

On the SW side i managed now to install an Oberon task in the loop. Would like to autostart it on reset/power up. Assume i have to rebuild the image on the SD card then, right? Would you tell me how to do?

When running on Embedded Project Oberon, SwitchTest.Run gives:
Switch 2 is on
Switch 3 is on
Switch 6 is on
Switch 7 is on

As my Nexys A7 board has 16 switches, I have changed SwitchCount = 16; but they do not show up?

Is it possible to attach and read in a USB keyboard directly when using Embedded Project Oberon on a Nexys A7 board?

Yes. If you have the Professional Edition you can confirm the order of module initialsation by disassembling the application and looking at the sequence of <modulename>..init calls in the initialisation code procedure (e.g. Blinker..init) of your application.

Does the module list in the 'map' file for a linked program represent their initialisation order, top to bottom?

I have installed Component Pascal and CPIde on my Windows 10 laptop. When I try to compile the simple "Hello World" example within CPIde I see: Unhandled Exception: System.NullReferenceException: Object reference not set to an instance of an object. at GPBinFiles.GPBinFiles.findOnPath(Char[] pathNam...

If I compile and run an example, then load and compile a different example, the run button runs the first example, not the one that was just compiled. Closing the IDE and opening it again allows the correct example to be launched via the run button. This seems to be a persistent phenomenon.

I noticed that the port `adr` for the RAM module is 18bits, whilst it's driving signal RISC5.v is 24bits. I was hoping you could tell me how that's resolved during synthesis? Are only the 18LSB used?