Search found 60 matches

by gray
Tue May 21, 2019 11:13 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: push {}
Replies: 20
Views: 15500

Re: push {}

FWIW, here's an improved version of the stack trace procedure. PROCEDURE stackTrace(fpAddr: INTEGER; VAR trace: Trace); VAR lr, stopAt: INTEGER; BEGIN trace.count := 0; stopAt := LinkOptions.StackStart - 8; SYSTEM.GET(fpAddr, fpAddr); WHILE (fpAddr < stopAt) & (trace.count # TraceDepth) DO SYSTEM.GE...
by gray
Fri May 17, 2019 7:01 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: push {}
Replies: 20
Views: 15500

Re: push {}

Good hint, thanks. For the module with the run-time error (I only consider run-time error exceptions here, not hardware fault exceptions), the compiler/linker embeds the source line number right in the code at the return address, so that case is covered. The modules in the stack trace need another a...
by gray
Thu May 16, 2019 3:13 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: push {}
Replies: 20
Views: 15500

Re: push {}

I see. Thanks for the clarification. May I place a feature request here? If yes, I'd like an extended ResData (".ref") that not only gives the name for a module's address range, but also the procedure names (with address range) within the module.
by gray
Tue May 14, 2019 10:19 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: push {}
Replies: 20
Views: 15500

push {}

I am dabbling with getting a stack trace upon run-time errors. For this, I obviously need to understand the structure of the stack when entering the error handler (SVC call). A related questions about interrupt handlers in general. PROCEDURE runtimeErrorHandler[0]; BEGIN . 632 E92D0000H push { } . 6...
by gray
Sat May 11, 2019 3:45 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: Type Test Inconsistency?
Replies: 5
Views: 4819

Re: Type Test Inconsistency?

Thanks, I have changed my code to use pointers now. As you say, it's clearer and cleaner.

Just out of interest, in the case without having the parameter for P1 declared as VAR, shouldn't the compiler flag the call to P2 from P1, as a read-only variable (p.t) is passed to a VAR parameter in P2?
by gray
Sat May 11, 2019 3:24 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: Adjustable Buffers, Number and Sizes
Replies: 2
Views: 3096

Re: Adjustable Buffers, Number and Sizes

Thanks. Yes, agreed. Maybe a default config module can make sense for library modules that work without required configuration, but could be tweaked for specific cases, eg. the buffer sizes for a serial driver. But if config is required, there shouldn't be a default config module.
by gray
Fri May 10, 2019 11:43 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: Adjustable Buffers, Number and Sizes
Replies: 2
Views: 3096

Adjustable Buffers, Number and Sizes

I have several library modules that are basically application-independent, apart from the number of buffers and the buffer sizes. Arrays are easy and well performing data structures for buffers, but they are of a fixed size. For maintenance reasons, I would prefer to configure these library modules ...
by gray
Sat May 04, 2019 3:49 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: Type Test Inconsistency?
Replies: 5
Views: 4819

Re: Type Test Inconsistency?

Assume P2 is implemented in another module, say implementing T and its extensions (my actual use case); the code is perfectly valid with a qualident as case variable. Now a module client calls P2 "wrongly", and P2 fails silently. But the test-case should execute correctly with an IS type test. PROCE...
by gray
Fri May 03, 2019 1:17 pm
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: Type Test Inconsistency?
Replies: 5
Views: 4819

Type Test Inconsistency?

From real-world code, distilled down to a test case: MODULE M; IMPORT Main, Out; TYPE T = RECORD i: INTEGER END; T1 = RECORD(T) k: INTEGER END; R = RECORD t: T1 END; P = POINTER TO R; VAR p: P; PROCEDURE P2(VAR t: T); BEGIN t.i := 13; Out.String("T"); Out.Ln; CASE t OF T1: t.k := 4; Out.String("T1")...
by gray
Tue Apr 30, 2019 5:53 am
Forum: Astrobe for ARM Cortex-M3, M4 and M7
Topic: 7.0.1 Fixes
Replies: 1
Views: 2671

7.0.1 Fixes

Type tests on expressions (e.g. array elements and individual fields of records) are handled correctly in IS expressions. Type tests using CASE statements can only be performed on (qualified) identifiers, not expressions. 1) Does this apply to all type tests, or only in leaf procedures? 2) Is deref...