Cmod A7-35T Progress

General discussions about using the Astrobe IDE to program the FPGA RISC5 cpu used in Project Oberon 2013

Cmod A7-35T Progress

Postby Helpdesk » Wed May 03, 2017 2:53 am

Regarding the very cool RISC5 Embedded Project Oberon, I wondered whether you've managed to make any further progress on the Cmod-a7-35T version?

Specifically, some progress in 1) access to the (512K) SRAM on the Cmod-a7-35T as with the original Project Oberon and Magnus' Pepino boards ? (From the Docs/Forum I understand Embedded Oberon RISC5 code runs only inside 192K BRAM of the FPGA right now). I looked and see the SRAM is mentioned in the Verilog Config file - but not yet hooked up, I think...

and 2) in adding I2C, maybe as you did with Magnus for Pepino with an I2C controller or even via bit-banging?
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Re: Cmod A7-35T Progress

Postby cfbsoftware » Wed May 03, 2017 8:29 am

The 512K SRAM on the Cmod A7-35T only has 8-bit wide access which limits its performance in a 32-bit system like RISC5 Oberon. If you want I2C Master capabilities and access to more RAM in a RISC5 system I recommend that you try Saanlima's Pepino Oberon board.

You will also need a Cortex-M3/M4 version of Astrobe with source code if you want to use the Astrobe I2C library module on a RISC5 system and our support to get it going.
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