Search found 423 matches
- Wed Apr 07, 2021 11:23 am
- Forum: Bug Reports
- Topic: INC and DEC fails when used in RECORDS
- Replies: 1
- Views: 113
Re: INC and DEC fails when used in RECORDS
The fix for this problem is now available in v7.2.3 Astrobe for Cortex-M3, M4 and M7.
- Wed Apr 07, 2021 11:14 am
- Forum: Astrobe for ARM Cortex-M3, M4 and M7
- Topic: v7.2.3 Astrobe for Cortex-M3, M4 and M7 have been released
- Replies: 0
- Views: 104
v7.2.3 Astrobe for Cortex-M3, M4 and M7 have been released
Minor maintenance upgrades v7.2.3 Astrobe for Cortex-M3, M4 and M7 have now been released. See What's New in Astrobe for Cortex-M3, M4 and M7 for a summary of the new features and bug-fixes since v7.0. If you are a registered user of the Professional or Personal Editions and your support period has ...
- Wed Mar 17, 2021 12:37 am
- Forum: Astrobe for FPGA RISC5
- Topic: What happens to out of range memory addresses?
- Replies: 1
- Views: 175
Re: What happens to out of range memory addresses?
Memory addressing limits are defined in Bootload.Mod. For the Artix-7 XC7A35T, using 192KB BRAM, MemLim is defined as 030000H. Read Section 8 Storage layout and management in the Project Oberon documentation (Astrobe menu > Help > Project Oberon) to see how the address range is partitioned and manag...
- Mon Mar 15, 2021 8:59 pm
- Forum: Astrobe for FPGA RISC5
- Topic: RAM port connection
- Replies: 1
- Views: 131
Re: RAM port connection
Yes - that is my understanding. Vivado issues the warning: width (24) of port connection 'adr' does not match port width (18) of module 'RAM' If you prefer you can modify the adr parameter in the RAM statement in RISC5Top.v to match the address width actually used in the RAM module for your particul...
- Fri Mar 12, 2021 8:20 am
- Forum: Bug Reports
- Topic: Summary of bug fixes since v7.0
- Replies: 0
- Views: 150
Summary of bug fixes since v7.0
See What's New in Astrobe for Cortex-M3, M4 and M7 for a summary of bug-fixes since v7.0.
- Tue Mar 09, 2021 9:24 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Why are the SPI MISO and SCLK signals shorted together?
- Replies: 2
- Views: 160
Re: Why are the SPI MISO and SCLK signals shorted together?
My understanding is that only one SPI device on the RISC5 system is active at any time. In section 17.2.3. The SPI interface for the SD-card (disk) and the Net of the book Project Oberon - The Design of an Operating System, a Compiler, and a Computer. it states: Here, however, no use is made of SPI'...
- Wed Mar 03, 2021 11:04 pm
- Forum: RISC5
- Topic: Measure Temperature and Humidity using Digilent's Pmod HYGRO
- Replies: 0
- Views: 200
Measure Temperature and Humidity using Digilent's Pmod HYGRO
The attached source code shows how to measure temperature and humidity via I2C using Digilent's Pmod HYGRO board.
It should work on any of the development boards with I2C that are supported by v7.2 Astrobe for RISC5.
It should work on any of the development boards with I2C that are supported by v7.2 Astrobe for RISC5.
- Wed Mar 03, 2021 10:59 pm
- Forum: Cortex-M3
- Topic: Measure Temperature and Humidity using Digilent's Pmod HYGRO
- Replies: 0
- Views: 183
Measure Temperature and Humidity using Digilent's Pmod HYGRO
The attached source code shows how to measure temperature and humidity via I2C using Digilent's Pmod HYGRO board . It was been tested on STMicroelectronics Nucleo-L152RE development board but should work with little or no modification on any of the development boards with I2C that are supported by v...
- Tue Dec 29, 2020 11:48 pm
- Forum: Astrobe for FPGA RISC5
- Topic: Project Oberon Workstation on Artix 7-100T
- Replies: 0
- Views: 972
Project Oberon Workstation on Artix 7-100T
To help new users get started we have now made available, free of charge, a disk image and Verilog bitstream files specifically to run the Project Oberon Workstation on the Digilent Nexys A7-100 FPGA trainer board 'out-of-the-box'. This release is based on the Oberon sources (as at March 2020) and V...
- Fri Dec 18, 2020 10:21 pm
- Forum: Astrobe for FPGA RISC5
- Topic: RISC5 Oberon now on the Artix 7-100T
- Replies: 0
- Views: 1040
RISC5 Oberon now on the Artix 7-100T
We have successfully implemented Astrobe Embedded Project Oberon on the XC7A100T FPGA device of the Xilinx Artix 7 family. This means that Astrobe can have 480 KBytes of RAM available to it. This is 2-3 times more than our other supported implementations, allowing for more / larger applications to b...