Search found 35 matches

by Helpdesk
Tue Feb 22, 2022 10:05 pm
Forum: CPIde and Component Pascal
Topic: Run button behaviour?
Replies: 1
Views: 6690

Run button behaviour?

If I compile and run an example, then load and compile a different example, the run button runs the first example, not the one that was just compiled. Closing the IDE and opening it again allows the correct example to be launched via the run button. This seems to be a persistent phenomenon.
by Helpdesk
Mon Mar 15, 2021 8:41 pm
Forum: Astrobe for FPGA RISC5
Topic: RAM port connection
Replies: 1
Views: 9727

RAM port connection

I noticed that the port `adr` for the RAM module is 18bits, whilst it's driving signal RISC5.v is 24bits. I was hoping you could tell me how that's resolved during synthesis? Are only the 18LSB used?
by Helpdesk
Fri Sep 04, 2020 6:12 am
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: Can the limit on the number of record extension levels be increased?
Replies: 1
Views: 13603

Can the limit on the number of record extension levels be increased?

We are using the "Record- Inheritance" quite intensively. Unfortunately, this is now limited to a depth of 4. Would it be a big deal to increase this to something a bit higher like 8 or 16?
by Helpdesk
Mon Oct 01, 2018 12:09 am
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: HCFiler for Cortex-M4
Replies: 1
Views: 12305

HCFiler for Cortex-M4

what are the likelyhood of your HCFiler software running OK on the Nucleo-STM32L432KC ? I have only found HCFiler posted for the M3 on the Forums. I'm guessing the code's likely to work, but again thought I'd better ask first in case you've already tried it on M4.
by Helpdesk
Wed Jun 27, 2018 8:23 am
Forum: Astrobe for FPGA RISC5
Topic: How to create a new user program file?
Replies: 1
Views: 12354

How to create a new user program file?

Odd thing on the Pepino board, I can load existing Oberon source system files from the Saalima SD card and edit them and compile and rum, but I haven't figured out how to create a user program file, such as a test "Hello World" or something basic,

I must be missing something.
by Helpdesk
Fri Sep 22, 2017 8:41 am
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: HCFiler compiling problems
Replies: 1
Views: 15644

HCFiler compiling problems

Trying to build with Astrobe for LPC1769, the project HCTest from HCFiler I get the errors attached below, related to type errors. I've also discover in the version for STM32an error on SPI.mod, related at first to the first pipe on the CASE. I'm trying to put to work HCFiler on LCPXpresso/mbed Base...
by Helpdesk
Wed May 03, 2017 2:53 am
Forum: Astrobe for FPGA RISC5
Topic: Cmod A7-35T Progress
Replies: 1
Views: 14576

Cmod A7-35T Progress

Regarding the very cool RISC5 Embedded Project Oberon, I wondered whether you've managed to make any further progress on the Cmod-a7-35T version? Specifically, some progress in 1) access to the (512K) SRAM on the Cmod-a7-35T as with the original Project Oberon and Magnus' Pepino boards ? (From the D...
by Helpdesk
Tue Feb 28, 2017 12:19 pm
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: Cortex-M7 Traps
Replies: 1
Views: 15277

Cortex-M7 Traps

The Traps section in Oberon for Cortex-M7 Microcontrollers refers to 'the Interrupt Handlers section above' but there doesn't appear to be such a section - I'm interested in how to write these.
by Helpdesk
Tue Feb 28, 2017 11:13 am
Forum: Astrobe for ARM Cortex-M0, M3, M4 and M7
Topic: SPI and I2C for Cortex-M7
Replies: 1
Views: 15042

SPI and I2C for Cortex-M7

Great to see the release of Astrobe for M7. I’ve read the manual and both the software and the M7 look great. The M7 with its higher clock and the larger 512K SRAM is much more modern and capable than the ‘smaller’ M4/M3 chips. However, I can’t find support for I2C or SPI in the manual - are these w...
by Helpdesk
Sun Jan 03, 2016 9:24 pm
Forum: Astrobe for FPGA RISC5
Topic: Changing the embedded OS memory map
Replies: 1
Views: 16620

Changing the embedded OS memory map

Practical projects need BRAM aside of program memory; so, use 96% or more of available BRAM is prohibitive. For example, if I try to test a FIR in hardware the embedded OS does not have enough BRAM available for data buffer and coefficients storage. Also due to BRAM tiles in different FPGA architect...