Nexys board RAM interface

[Helpdesk]

The Nexys.xcd file - to my knowledge - defines the periphery of the Artix FPGA, which means the pinout.

Now i'm really wondering where the memory link (inbus, outbus, adressbus) is set? i simply find no definition for it in the file?

[cfbsoftware]

The RISC5 RAM interface is described in Chapter 17 The processor's environment in the book Project Oberon - The Design of an Operating System, a Compiler, and a Computer.

Although the details are different, the basic principles of the design for the Artix 7 FPGA on the Digilent Nexys board are the same as for the Spartan-3 FPGA used in the original implementation of Project Oberon 2013.

[daniel]

Okay, found it in Project Oberon and also in the Verilog source, but assume it should be somewhere in the .xcd-File too?

[cfbsoftware]

OK - now read the Nexys-A7 Reference Manual. If you still do not understand why the .xcd file is not involved you should be able to get help on the Digilent Forum.