RAM port connection

General discussions about using the Astrobe IDE to program the FPGA RISC5 cpu used in Project Oberon 2013
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Helpdesk
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RAM port connection

Post by Helpdesk » Mon Mar 15, 2021 8:41 pm

I noticed that the port `adr` for the RAM module is 18bits, whilst it's driving signal RISC5.v is 24bits. I was hoping you could tell me how that's resolved during synthesis? Are only the 18LSB used?

cfbsoftware
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Re: RAM port connection

Post by cfbsoftware » Mon Mar 15, 2021 8:59 pm

Yes - that is my understanding. Vivado issues the warning:
width (24) of port connection 'adr' does not match port width (18) of module 'RAM'

If you prefer you can modify the adr parameter in the RAM statement in RISC5Top.v to match the address width actually used in the RAM module for your particular development board. e.g. in your case you should change it to

Code: Select all

.adr(adr[0:17])

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