SYSTEM.BIT Problem

[gray]

Consider this code snippet

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  REPEAT UNTIL SYSTEM.BIT(MCU.XOSC_STATUS, 31)

and the corresponding assembly code:

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.   158    09EH  04808H          ldr      r0,[pc,#32] -> 192
.   160    0A0H  06801H          ldr      r1,[r0]
.   162    0A2H  0D5FCH          bpl.n    -8 -> 158

.   192  <Const: 040024004H  040024004H>

The procedure hangs at that point, unsurprisingly. To be clear, the hardware bit is set (it's the crystal oscillator on the RP2040), as confirmed with this workaround:

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    REPEAT
      SYSTEM.GET(MCU.XOSC_STATUS, x)
    UNTIL 31 IN BITS(x)

Testing the boundaries:

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    REPEAT UNTIL SYSTEM.BIT(MCU.XOSC_STATUS, 30);
.   158    09EH  04808H          ldr      r0,[pc,#32] -> 192
.   160    0A0H  06801H          ldr      r1,[r0]
.   162    0A2H  00049H          lsls     r1,r1,#1
.   164    0A4H  0D5FBH          bpl.n    -10 -> 158

This (incorrect) code

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  REPEAT UNTIL SYSTEM.BIT(MCU.XOSC_STATUS, 32)

results in a compiler exception:

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System.Exception: "Assertion failure ORG.cp:597"
   at ORG.ORG.Put16Shift(Int32 op, Int32 dst, Int32 src, Int32 imm)
   at ORG.ORG.Bit(Item& x, Item& y)
   at ORP.ORP.StandFunc(Item& x, Int32 fct, Boxed_TypeDesc restyp, Int32 nfp)
   at ORP.ORP.factor(Item& x)
   at ORP.ORP.term(Item& x)
   at ORP.ORP.SimpleExpression(Item& x)
   at ORP.ORP.expression(Item& x)
   at ORP.ORP.StatSequence()
   at ORP.ORP.ProcedureDecl()
   at ORP.ORP.Module()
   at Compiler.Compiler.Compile(String source, Writer w, Int32& errcnt)

Which may or may not give a hint to the point of the problem. :)

[cfbsoftware]

Thank you for your report. The RP2040 clock initialisation statement:

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CONST
  (* XOSC_STATUS *)
  STABLE  = 31;
 ...
  REPEAT UNTIL SYSTEM.BIT(MCU.XOSC_STATUS, STABLE);

Should generate code that looks something like this:

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.    30    01EH  04803H          ldr      r0,[pc,#12] -> 44
.    32    020H  06801H          ldr      r1,[r0]
.    34    022H  00009H          movs     r1,r1
.    36    024H  0D5FBH          bpl.n    -10 -> 30
...
.    44  <Const: 040024004H  040024004H>

Unfortunately the Cortex-M0 code generator optimised out the instruction: movs r1, r1
In most cases the optimisation is valid but in this particular instance the instruction is required to set the condition code correctly. The problem will be fixed in the next Cortex-M0 maintenance release. In the meantime you can use your suggested workaround.