Project Oberon FPGA RISC5 Workstation
Nexys A7-100 FPGA Trainer board: SDHC Disk Image (Dec 2020)
The Project Oberon Workstation operating system is described in an article titled Oberon System Implemented on a Low-Cost FPGA Board which was published in Issue 91, Second Quarter 2015, of Xilinx's Xcell Journal.
It is also documented in detail in the book Project Oberon - The Design of an Operating System, a Compiler, and a Computer. Revised Edition 2013 Niklaus Wirth Jürg Gutknecht. ISBN 0-201-54428-8
We distribute the Oberon compiler, executable and source code files of the Project Oberon operating system on an SDHC disk image for no charge. This is for the convenience of those who want to use Project Oberon on an actual FPGA development board using off-the-shelf components 'out-of-the-box'.
The Oberon Workstation was designed to be used on FPGA development boards equipped with 1 MB of RAM. Unfortunately these are no longer available. Most newer boards use external DRAM memory which is much more difficult to interface, requiring circuits for refresh and initialization (calibration). The resulting Verilog code can be as complex as the entire processor with SRAM. A simpler alternative is to use internal BRAM (block RAM) which resides on the FPGA chip itself. However, it is only recently that affordable boards have become available with sufficient BRAM to run Project Oberon.
We have now succeeded in implementing Project Oberon on the Digilent Nexys A7-100 FPGA Trainer board. The BRAM available was limited to 512 KB (instead of the usual 1 MB) which did present some challenges. However, it proved to be sufficient to be able to use the system to compile itself, using all of the standard Project Oberon modules.
The Nexys A7 board is connected to a 1024 x 768 @ 70Hz VGA display, a PC keyboard connected via the USB HID socket, and a 3-button PS/2 mouse via a Digilent PS/2 Pmod adapter. The SDHC card is inserted into the microSD socket under the board. A PS/2 keyboard could be used with an additional Pmod adapter or swapped with a 3-button USB mouse. It would only be necessary to change a few lines in the constraints file and regenerate the FPGA 'bitstream' file to do this.
Once you have installed the image on an SDHC card you can use it to boot and run the Project Oberon workstation system on the Digilent Nexys A7-100 FPGA development board that has been programmed with the RISC5 Verilog files which are also included with the disk image.
Oberon software development can then be carried out using Project Oberon's screen editing and compilation features without using Astrobe, Windows or any other operating system.
Embedded Project OberonAn alternative approach for developing Oberon software to target the RISC5 processor is to use Astrobe for FPGA RISC5, a free Windows 10 development system that developers can use to edit and cross-compile Oberon applications. The compiled applications produced by Astrobe can be uploaded to the host FPGA RISC5 target development board via a fast RS232 link from the PC to run on a subset of Project Oberon 2013.
Go to the Embedded Project Oberon page for more information .
Comparison with Standard Project Oberon
The Oberon language source code that was used to build the Project Oberon system, compiler and applications was downloaded from Professor Wirth's site. The latest update date of any of the source code files is 9.3.2020 (ORB.Mod)
The only change made to any of the Oberon source code files was an additional statement in Modules.Free to allow more efficient use of the available modules space whenever the most recently loaded module is unloaded. This should minimise the occurrence of "insufficient space" errors when an attempt to run a command of a module that is not already loaded.
The differences between the implementation of Project Oberon on the Nexys A7-100 and the standard Project Oberon workstation system are:
|Clock||25 MHz||37.5 MHz|
1280 x 768
1280 x 768
|Global Data +
|512 KB||264 KB|
|Video RAM||96 KB||96 KB|
|Dynamic Data||415 KB||150 KB|
Changes to the Verilog code are:
|Module||No of lines
|RAM.v||91||New module to use BRAM instead of SRAM. This is based on
the original written by Magnus Karlsson of Saanlima Electronics.
|RISC5Top.v||35||External pixel clock, faster clock speed, no SRAM etc.|
|VID.v||5||Pixel clock generation|
|RS232R.v||1||Faster clock speed|
|RS232T.v||1||Faster clock speed|
|SPI.v||1||Faster clock speed|
The Project Oberon Workstation SDHC image and Verilog sources are currently available free of charge for the following development board:
Board FPGA Xilinx Part Manufacturer Nexys A7-100 Artix 7 XC7A100T-1CSG324C Digilent
The complete Project Oberon FPGA RISC5 Workstation software system consists of:
- A MicroSDHC disk image file containing the Project Oberon OS with sources
- A bitstream file to program the RISC5 processor on the target FPGA processor
- Verilog sources to customise the RISC5 system if desired
WARNING: This should be considered to be an unstable release of Project Oberon for experimental use only. Because it only has access to half of the RAM that it was designed to use it is likely to crash and lose data if an application attempts to use more resources than are available. We do not recommend purchasing a Nexys A7-100 board specifically to run Project Oberon. You should only consider using this version if you already have a Nexys A7-100 or intend to use it for other purposes as well.
Request your copy via email You should receive an email with your download instructions within 2 business days.
If you have any questions about this system ask them on the Astrobe for FPGA RISC5 Forum. You will also find the latest news and implementation details there.